Mentor Graphics Boosts Eldo Simulator Performance with Generalized Multi-Threading Technology
04 11์ 2008 - 11:00PM
Business Wire
Mentor Graphics Corporation (Nasdaq: MENT) today announced a new
version of the Eldo๏ฟฝ transistor-level analog simulator that offers
improved raw speed performance without compromising accuracy. The
speed up targets very large post-layout simulations that are
mandatory at 45nm processes and below to thoroughly verify a
complex design. Final verification simulations routinely include
hundreds of thousands of devices and millions of coupled parasitic
devices originating from complex layout extraction. Two key
synergetic improvements to the Eldo simulator have been developed
to address the new paradigm of matrices with millions of coupling
elements. First, an entirely revised matrix solving strategy
provides dramatic speed up over the previous version. Second, new
and highly scalable multi-threading technology allows users to take
advantage of inexpensive multi-CPU hardware. Using four CPUs, the
observed speed up ranged between 3X to 10X depending on the circuit
๏ฟฝsignature๏ฟฝ in terms of the ratio of active devices to parasitic
elements. The new architecture was validated on thousands of
circuits ranging from ๏ฟฝsmall๏ฟฝ phase-locked-loops or converters to
much larger power management circuits or DRAM circuits. On average,
larger circuits experienced a greater speed up. The speed up also
opens the door for circuits that were simply too large to simulate
with genuine SPICE level accuracy. Now, power nets or clock trees
become reasonable targets for this level of simulation. At the 45nm
node, not only are post-layout simulations mandatory to avoid
silicon re-spins, but these simulations have to retain the full
details of the carefully extracted interconnect couplings. Many of
these parasitic elements appear small, but when hundreds of them
are combined, the impact upon performance or even functionality can
be devastating. ๏ฟฝWhen developing this project, compromising
simulation accuracy was not an option,๏ฟฝ said Jue-Hsien Chern, vice
president and general manager, Mentor Graphics. ๏ฟฝWhen IC designers
have spent considerable effort obtaining an accurate post-layout
netlist, they don๏ฟฝt want a SPICE simulator to ๏ฟฝsimplify๏ฟฝ or ignore
the parasitic elements. The task of a reliable analog simulator is
not to silently manipulate the input netlist until it can compute
some approximate waveforms in a reasonable CPU time. We listened to
our customers and developed the right technologies to meet their
challenge. Combining advanced math and sophisticated computer
science, we developed a dedicated matrix solving technology
amenable to efficient, generalized multi-threading. Not a single
parasitic coupling capacitance is ignored and not a single digit of
precision is lost.๏ฟฝ Designers benefit because the entire simulation
process that includes matrix solving and device evaluations is now
efficiently multi-threaded, and the speed up scales well with the
number of CPUs. Since no tuning of the process is necessary, the
improvements translate into a measurable net increase of
productivity and/or verification coverage. The new technology is
fully and transparently integrated into the ADVance MS๏ฟฝ (ADMS)
tool, Mentor๏ฟฝs single-kernel, language-neutral functional
verification environment for digital, analog, mixed-signal and RF
circuits. The new release of the simulator is part of the AMS
2008.2 release. AMS Simulation Technology from Mentor Graphics The
Mentor ADMS tool is a single-kernel, language-neutral functional
verification environment for digital, analog, mixed-signal and RF
circuits. This platform is built upon four high-performance,
customer-proven simulation technologies: the Eldo tool for analog,
ModelSim๏ฟฝ for digital, ADiT๏ฟฝ for transistor-level, and Eldo RF for
radio frequency simulations. ADMS supports most of the design
languages, including VHDL, VHDL-AMS, Verilog, Verilog-AMS, SystemC,
SystemVerilog, Spice, and C, for the design and verification of
mixed-signal system, and SoC. ADMS has gained wide acceptance since
its introduction and is currently used in hundreds of customer
sites. About Mentor Graphics Mentor Graphics Corporation (Nasdaq:
MENT) is a world leader in electronic hardware and software design
solutions, providing products, consulting services and
award-winning support for the world๏ฟฝs most successful electronics
and semiconductor companies. Established in 1981, the company
reported revenues over the last 12 months of about $850 million and
employs approximately 4500 people worldwide. Corporate headquarters
are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon
97070-7777; Silicon Valley headquarters are located at 1001 Ridder
Park Drive, San Jose, California 95131-2314. World Wide Web site:
http://www.mentor.com/. Mentor Graphics, ModelSim and Eldo are
registered trademarks and ADVance MS and ADiT are trademarks of
Mentor Graphics Corporation. All other company or product names are
the registered trademarks or trademarks of their respective owners.
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