WILSONVILLE, Ore., Sept. 9, 2015 /PRNewswire/ --
Highlights:
- The Unified Power Format (UPF) Successive Refinement
Methodology enables the incremental specification and early
verification of power management intent.
- The Questa® Power Aware Simulation solution and
Visualizer Debug Environment facilitate adoption of a Successive
Refinement Methodology flow.
- ARM has demonstrated support for Successive Refinement in a
complete IP to SoC design flow from verification to
implementation.
Mentor Graphics Corporation (NASDAQ: MENT) today
announced support for the Low Power Successive Refinement
Methodology using Questa Power Aware Simulation and new
capabilities in the Visualizer Debug Environment to dramatically
improve verification re-use and productivity for low power designs
using ARM technology®.
![Mentor Graphics logo. Mentor Graphics logo.](http://photos.prnewswire.com/prnvar/20140317/AQ83812LOGO)
UPF, which specifies 'power intent' separate from the design, is
used in both the verification and implementation stages of chip
design. Traditional low power methodologies that focus on
implementation start to break down as complex power management
requirements increase. The Successive Refinement Methodology
defines power intent more abstractly early in the design cycle, and
refines/augments it in more detail as the design moves to
implementation. This improves the overall verification process
and the reuse of verification results at each step. The
Successive Refinement Methodology focuses on dividing UPF into
Constraint UPF for IP/blocks, Configuration UPF for verification
and Implementation UPF. This enables soft IP and sub-systems
to be developed from multiple sources (along with their power
intent) and then quickly verified together to preserve equity in
power verification.
The Successive Refinement Methodology was introduced into the
UPF specification by John Biggs,
senior principal research engineer, ARM and chair of IEEE1801.
Mentor and ARM have worked closely on the Successive Refinement
Methodology since its inception. This collaboration has resulted in
ARM delivering Constraint UPF and example Configuration UPF for ARM
IP for a flow verified with Questa Power Aware Simulation and
completed through implementation (synthesis and place and
route).
"Delivering increasingly energy-efficient processor IP, in the
fast-paced markets that ARM operates in, leads to a constant demand
for new process optimization tools," said John Biggs, senior principal engineer, ARM and
chair of IEEE1801. "By using the Successive Refinement Methodology,
ARM is able to deliver IP built for low power applications
alongside a UPF description of the
technology-independent power intent. This allows our partners
to dramatically reduce their low power verification cost and
time."
"Mentor has been driving low power standards from the inception
with UPF. The collaboration with ARM that resulted in the
Successive Refinement Methodology enables a much needed
'shift-left' to address the growing complexities of low power
verification," said John Lenyo, vice
president and general manager, Design Verification Technology
Division, Mentor Graphics. "Questa Power Aware Simulation comes
with native UPF2.1 support, automatic low power checks and
coverage. Coupled with unique exploration of the power management
structures and behaviors with the Visualizer Debug Environment, it
accelerates and automates low power verification flows using the
Successive Refinement Methodology."
About the Questa Functional Verification platform
The
Questa Functional Verification platform is a core technology in the
Mentor® Enterprise Verification Platform (EVP) – a platform that
boosts productivity in ASIC and SoC functional verification by
combining cutting-edge verification technologies in a cohesive
verification platform.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic
hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronic, semiconductor and systems companies.
Established in 1981, the company reported revenues in the last
fiscal year in excess of $1.15
billion. Corporate headquarters are located at 8005 S.W.
Boeckman Road, Wilsonville, Oregon
97070-7777. World Wide Web site: http://www.mentor.com/.
Mentor Graphics and Questa are registered trademarks of Mentor
Graphics Corporation. All other company or product names are the
registered trademarks or trademarks of their respective owners.
For more information,
please contact:
|
David Smith
Mentor Graphics
503.685.1135
david_smith@mentor.com
|
|
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SOURCE Mentor Graphics