Mentor Graphics HDL Designer Saves Months of Design Effort with Concurrent HDL Checking
07 10월 2005 - 10:00PM
Business Wire
Mentor Graphics Corporation (Nasdaq:MENT), the leader in
standards-based digital IC design creation, analysis, synthesis,
and management tools, today announced the release of a new
concurrent design checking and creation environment, available in
the latest version of the HDL Designer Series(TM) tool suite.
Widely adopted as the most effective HDL design solution for ASICs
and FPGAs, the comprehensive HDL Designer Series environment
equally benefits individual engineers as well as large design
teams, significantly reducing cycle times and re-spins. "From a
company perspective, the overall benefit using HDL Designer Series
is the increase in designer productivity," said Thierry Pfirsch,
competency manager, Hardware Design Tools, Alcatel Worldwide. "We
have seen significant improvement in the time needed to capture,
check, analyze, debug and document designs, in some cases up to
five times faster than before." With this new release, HDL Designer
fully integrates the industry's first high-speed HDL design
checking engine, optimized to operate real-time and concurrently
during design creation. The release also supports advanced design
and verification languages such as SystemVerilog and Property
Specification Language (PSL), and provides expanded documentation
capabilities via Adobe Systems' Scalable Vector Graphics (SVG)
output. "Our primary motivation in acquiring HDL Designer Series
was to gain access to its design entry and visualization tools,
which allow us to work a higher level than just VHDL or Verilog
text entry," said Laurent Hausammann, senior EE engineer, ASIC team
leader, Olivetti I-Jet. "Using the tool's various features saves us
many months of effort across the entire design cycle." Immediately
available for use by ASIC and FPGA design teams working with
Verilog, SystemVerilog, and VHDL design languages, the integrated
static design checking functionality enables designers using HDL
Designer to accurately analyze RTL code during design creation,
where they can quickly identify and resolve rule violations that
would otherwise cause re-spins in simulation and synthesis runs or,
ultimately, re-spins in silicon. "Concurrent design checking
fundamentally changes the design paradigm. This is analogous to the
way in which spelling and grammar checkers have changed the way we
create written correspondence, sharply reducing the need for manual
review," said Glenn Perry, general manager, Design Creation
Business Unit, Mentor Graphics. "Our approach to concurrent design
checking, combined with blazing fast speed of analysis and error
isolation, enables companies to identify and rectify potential
defects before they become more expensive to fix downstream."
Unlike traditional post-process, batch-oriented linting tools, the
configurable, high-performance HDL checking features in HDL
Designer are easy to use and extraordinarily fast, thus enabling
real-time analysis. The parameterized rule capability makes it far
easier to configure the tool to do what any particular design team
needs without initially spending a lot of time preparing rule sets.
Moreover, checking for design reusability when the code is
originally written helps deliver the productivity promise of reuse,
by reducing the need to change and re-verify the code for every
subsequent design in which it is used. About HDL Designer Series
The HDL Designer Series tool suite provides a complete
enterprise-level HDL development platform for ASICs and FPGAs,
which integrates easily into any existing design flow. HDL Designer
Series enables companies to scale organizational productivity, as
well as engineering productivity, by providing an impressive array
of technologies focused on design creation, analysis, checking, and
management capabilities within a single tool. HDL Designer Series
is part of Mentor Graphics(R) comprehensive FPGA Advantage(R)
design flow, which also includes the industry-leading ModelSim(R)
and Precision(R) Synthesis tools. Pricing and Availability HDL
Designer Series is available immediately with pricing starting at
$6400 USD for a node-locked license and $9600 USD for a floating
license. HDL Designer Series is compatible with all major operating
systems for maximum flexibility and ease-of-use. The following
platforms are currently supported: Linux Redhat/SuSE, Sun Solaris,
HP-UX, and Windows 2000, XP, and NT 4.0. More information is
available at
www.mentor.com/products/fpga_pld/hdl_design/hdl_designer_series/.
About Mentor Graphics Mentor Graphics Corporation is a world leader
in electronic hardware and software design solutions, providing
products, consulting services and award-winning support for the
world's most successful electronics and semiconductor companies.
Established in 1981, the company reported revenues over the last 12
months of about $700 million and employs approximately 3,900 people
worldwide. Corporate headquarters are located at 8005 S.W. Boeckman
Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters
are located at 1001 Ridder Park Drive, San Jose, California
95131-2314. World Wide Web site: www.mentor.com. Mentor Graphics,
FPGA Advantage, ModelSim, and Precision Synthesis are registered
trademarks and HDL Designer Series is a trademark of Mentor
Graphics Corporation. All other company or product names are the
registered trademarks or trademarks of their respective owners.
Mentor Graphics Corp. (NASDAQ:MENT)
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