GLOBALFOUNDRIES Improves IC Reliability with Customized Circuit Checks Using Mentor Graphics Calibre PERC
22 5월 2012 - 10:00PM
Business Wire
Mentor Graphics Corp. (NASDAQ: MENT) today announced that
GLOBALFOUNDRIES is helping its customers improve reliability
checking by adding Calibre® PERC to select 28nm bulk CMOS design
enablement flows. Calibre PERC will give designers access to the
new reliability verification rules developed by the IBM
Semiconductor Development Alliance (ISDA), augmented with
GLOBALFOUNDRIES specific checks to help prevent external latch-up.
Using Calibre PERC’s unique architecture, complex reliability rules
that require the integration of logical (net list) and layout (GDS)
information can be fully automated, eliminating manual
spreadsheet-based efforts and reducing the chances of design
errors.
“In the past, verification of latch-up immunity depended on
manual layout checks and rough approximations of device and
interconnect resistance using traditional mechanisms,” said Bill
Liu, vice president of design enablement at GLOBALFOUNDRIES. “Now
our customers can perform accurate measurements and analysis
automatically using Calibre PERC’s data integration capability. For
example, some of our customers are currently using PERC to
accurately determine the resistance of the paths in complex output
driver arrays as a function of device spacing. This allows them to
easily and accurately detect points in the circuit where latch-up
could be an issue and to make appropriate improvements.”
GLOBALFOUNDRIES’ 32/28nm solutions are based on the Gate First
HKMG technology that has reached high-volume production in the
company’s Fab 1 facility in Dresden, Germany. This approach to HKMG
offers advantages in terms of both scalability and
manufacturability, enabling full scaling from 40nm in area and
performance, while sharing the process flow, design flexibility,
design elements and benefits of all previous nodes based upon poly
SiON gate stacks.
The Calibre PERC product is capable of performing complex checks
needed to address reliability issues, including electrostatic
discharge (ESD), electrical overstress (EOS), errors arising from
signals crossing multiple power domains, and advanced electrical
rule checking (ERC) concerns. It is uniquely capable of revealing
electrical violations that might otherwise result in short-term,
long-term or even catastrophic electrical failure. It not only
detects violations, but provides designers with a holistic
environment for debugging circuit reliability problems with an
integrated view of circuit connectivity, topology, physical layout
and design rules that is not available in any other tool. Like
other Calibre products, the Calibre PERC solution uses the Mentor®
advanced SVRF and TVF (TCL verification) formats, for quick
implementation of customized checks to detect electrical design
issues.
“Calibre PERC is both highly customizable and user friendly,”
said Joe Sawicki, vice president and general manager of the
Design-to-Silicon Division at Mentor Graphics. “Moreover, it runs
on any netlist; it is integrated with the rest of the Calibre
product suite; and it is interfaced to all major design flows. So
it quickly delivers the trusted accuracy needed by designers to
produce world-class silicon solutions.”
About Mentor GraphicsMentor Graphics Corporation is a
world leader in electronic hardware and software design solutions,
providing products, consulting services and award-winning support
for the world’s most successful electronic, semiconductor and
systems companies. Established in 1981, the company reported
revenues in the last fiscal year of about $1,015 million. Corporate
headquarters are located at 8005 S.W. Boeckman Road, Wilsonville,
Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
(Mentor Graphics, Mentor and Calibre are registered trademarks
of Mentor Graphics Corporation. All other company or product names
are the registered trademarks or trademarks of their respective
owners.)
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