Mentor Graphics New Questa Verification Platform Functionality Drives Verification Throughput
20 2월 2013 - 11:00PM
Business Wire
Mentor Graphics Corp. (NASDAQ:MENT) today announced the 10.2
release of the Questa® functional verification platform, a tightly
integrated and extensible set of tools and solutions that is
transforming the functional verification of complex System-on-Chip
(SoC) and FPGA designs. This new release extends the Questa
Platform’s technology leadership in verification productivity with
performance improvements across the entire spectrum of engines and
solutions, unified debug, leading verification management and
analysis capabilities, and superior support of the latest
methodology and language standards.
Simulation Performance: As designs continue to grow in
size and complexity, the need for raw performance and smarter
simulation throughput remain a critical verification requirement.
The Questa 10.2 release delivers multiple performance improvements
in simulation—up to 3X in designs using SystemVerilog/OVM/UVM, up
to 5X with Questa Multi-Core Simulation, and up to 6X for Low Power
simulations with UPF. These simulation performance improvements,
coupled with the Questa Platform’s unique “compile once and
simulate often” architecture, and enhanced GUI read/write
performance, gives verification users optimum simulation
throughput.
Unified Debug: The Questa 10.2 release introduces new
technology that allows users to easily sync all analysis windows,
track forward and backward in time, and automatically trace issues
back to the original cause, dramatically reducing debug time and
increasing productivity. For UVM and SystemVerilog users, the
Questa 10.2 release has multiple new capabilities including a
dedicated UVM window, UVM native objects in all the major debug
windows, a Constraint Explorer, and UVM Register Assistant. All of
these enhancements extend the Questa Platform’s leading
SystemVerilog and UVM/OVM debug and automation support.
“AumRaj thoroughly reviewed and tested the new 10.2 advanced
features of the Questa Verification Platform including simulation,
debug, power aware simulation, and intelligent Testbench Automation
and are very impressed with the continuing growth of advanced
verification capabilities of Questa,” said Dipika Ganatra, director
at AumRaj Inc. “As verification consultants, we need to be able to
quickly and efficiently help our customers improve their
verification process and methodology and the leading-edge
technologies of the Questa platform enable us to do this.”
Verification Throughput: In addition to enhancing raw
simulation performance and debug, Questa 10.2 maximizes total
verification throughput by dramatically speeding up coverage
closure, results analysis, and regression management. To quickly
achieve project wide coverage metrics, Questa 10.2 combines
coverage data from directed, constrained random and intelligent
tests in addition to accelerating coverage ranking and merging up
to 6X. Questa Verification Management also monitors important
verification trends and metrics, automates test planning and
results analysis, and is fully supported on both Linux and Windows,
providing flexibility to choose a single environment for test
planning and simulation.
“Design teams are looking for solutions that increase overall
verification throughput, improve verification quality, speed up
adoption of new methodologies, and effectively analyze verification
results,” said John Lenyo, vice president and general manager of
the Design Verification Technology division of Mentor Graphics.
“The Questa functional verification platform contains an integrated
set of leading-edge technologies with high performance simulation
and debug at its core that addresses the major verification
challenges faced by today’s complex SoC, ASIC, and FPGA
designs.”
Leading Support of Standards: In addition to performance
and debug, standard languages and methodologies are essential for
advancing productivity in verification. The Questa 10.2 release
completes Mentor’s support for VHDL-2008 and adds support for the
recently ratified SystemVerilog/1800-2012 including enhanced cover
group specifications and generic interconnect. The Questa Platform
extends its leading support of UPF to enable a complete
system-level, low-power verification methodology, and delivers the
first native support for the newly ratified Accellera UCIS (Unified
Coverage Interoperability Standard).
“We are impressed to see how fast and comprehensive Mentor
implemented very useful key features of the recently released IEEE
1800-2012 SystemVerilog standard,” said Srini Venkataramanan, CTO
at CVC Pvt. “Our customers always demand the latest updates during
our regular training sessions. It is one thing to say that the LRM
has it, it is quite another to have it in their hands! We applaud
Mentor again as the leader in SystemVerilog implementation enabling
a fast adoption by the SystemVerilog users and the Questa Vanguard
Ecosystem.”
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic
hardware and software design solutions, providing products,
consulting services and award-winning support for the world’s most
successful electronic, semiconductor and systems companies.
Established in 1981, the company reported revenues in the last
fiscal year of about $1,015 million. Corporate headquarters are
located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
http://www.mentor.com/.
(Mentor Graphics and Questa are registered trademarks of Mentor
Graphics Corporation. All other company or product names are the
registered trademarks or trademarks of their respective owner.)
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