Mentor Graphics Announces Completion of 20 nm Test Chip Tapeout with STMicroelectronics Using Olympus-SoC Place and Route Sys...
04 11월 2011 - 10:00PM
Business Wire
Mentor Graphics Corporation (NASDAQ:MENT) today announced the
successful tapeout of a 20 nm test chip in collaboration with
STMicroelectronics, marking a significant milestone in the
development of a complete Mentor® design-to-silicon solution for
next-generation process technology. The test chip was implemented
using the Olympus-SoC™ place and route system, and verified using
the Calibre® nmDRC platform, which is the verification and double
patterning solution used by R&D teams at STMicroelectronics.
Together, the Olympus-SoC, Calibre and Tessent® silicon test and
yield analysis products provide a comprehensive flow for 20 nm IC
development.
“The Olympus-SoC place and route system has been proven on many
tapeouts across multiple nodes and different application areas,”
said Pravin Madhani, general manager of the Mentor Place and Route
Group. “The 20 nm node has a unique set of new requirements
including double patterning. Working with STMicroelectronics as a
teaching customer and strategic investment partner in the DeCADE
program has enabled us to make rapid progress in delivering
advanced implementation solutions for 20 nm enablement.”
The Olympus-SoC place and route system is a complete
netlist-to-GDSII system and is built on patented concurrent
multi-corner multi-mode (MCMM) optimization, high capacity data
model, advanced low power capabilities and integration with the
Calibre® platform for faster manufacturing closure. The OpenRouter
architecture of the Olympus-SoC product enables native invocation
of Calibre engines during design and uses the foundry signoff decks
to ensure that the resulting layout is decomposable for
multi-patterning, in addition to being DRC/LVS/DFM signoff
clean.
“Increased process complexity and variability, lithography
limitations, large design sizes and extreme low power add to the IC
design challenges at 20 nm,” said Philippe Magarshack, group vice
president at STMicroelectronics Technology Research and
Development. “Through the ISDA and the DeCADE joint development
program, we are working very closely with Mentor Graphics on
various aspects of 20 nm design enablement. We are pleased with the
Olympus-SoC integrated platform’s ability to deliver a 20 nm place
and route solution with high quality of results, which we recently
demonstrated on a 20 nm test chip tapeout. We consider this to be a
significant milestone toward demonstrating our 20 nm
readiness.”
About DeCADE
The joint-development project named DeCADE builds on advanced
design solutions for SoC (System-On-Chip) development. DeCADE
reinforces the Crolles cooperative R&D cluster, which gathers
partners that develop and enable low-power SoCs and value-added
application-specific technologies, and is a great example of a
project developed within the framework of the Nano2012 program.
Nano2012 is a strategic R&D program, led by STMicroelectronics,
which gathers research institutes and industrial partners and is
supported by French national, regional and local authorities.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ:MENT) is a world leader in
electronic hardware and software design solutions, providing
products, consulting services and award-winning support for the
world’s most successful electronic, semiconductor and systems
companies. Established in 1981, the company reported revenues over
the last 12 months of about $915 million. Corporate headquarters
are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon
97070-7777. World Wide Web site: http://www.mentor.com/.
(Mentor Graphics, Mentor, Calibre and Tessent are registered
trademarks, and Olympus-SoC is a trademark of Mentor Graphics
Corporation. All other company or product names are the registered
trademarks or trademarks of their respective owners.)
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