Mentor Graphics and TSMC Collaborate to Improve and Expand 20nm IC Physical Verification Offering
29 5월 2013 - 8:00AM
Business Wire
Mentor Graphics Corp. (NASDAQ:MENT) today announced significant
achievements in its continued collaboration with TSMC on 20nm
physical verification kit optimizations. This joint effort has
reduced Calibre® nmDRC™ 20nm signoff runtimes by at least a factor
of 3X and memory requirements by 60% compared to initial design
kits released last year. In addition, Calibre PERC™ N20 design kits
are now available to TSMC customers as part of the companies’
ongoing collaboration for IC reliability improvement. The
collaboration will continue as mutual customers ramp their releases
of N20 production designs, with the goal of maintaining rapid
turnaround on full-chip signoff runs for the largest SoC designs in
the industry.
The Calibre PERC kit for N20 includes new checks for latch-up
prevention and IO-ESD protection, and a number of multiple power
domain checks, which represent a significant step forward in
automating procedures that previously had to be done manually.
Moreover, by using both the Calibre PERC and Calibre nmDRC kits,
customers are able to quickly identify and correct voltage-aware
DRC violations, which is critical for today’s multi-voltage
advanced process designs.
Other ongoing collaboration between TSMC and Mentor is focusing
on optimizing the Calibre DFM product family, which incorporates
TSMC’s unified DFM (UDFM) engine. Improvements are expected to
result in runtime reduction in TSMC’s latest DDK release, and
customers who use any DFM tools compliant with TSMC UDFM engine
will benefit.
“Our work with TSMC demonstrates the advantage of close
collaboration among the foundry, EDA vendor and lead customers to
bring new process nodes to market more efficiently,” said Michael
Buehler-Garcia, senior director of Calibre Design Solutions
Marketing at Mentor Graphics. “Our efforts don’t stop when tools
are qualified. We continue to work with TSMC to optimize the design
kits as the process matures, resulting in overall shorter design
cycle times.”
“The close working relationship between TSMC and Mentor has
existed for many years and continues to result in new solutions and
rapid performance optimization,” said Suk Lee, TSMC senior
director, Design Infrastructure Marketing Division. “With N20 we
have taken our efforts to the next level to deliver optimized
Calibre DRC decks, which include multi-patterning, on an even
faster timetable than for prior nodes. Building on this success we
have already extended performance improvements to the first-release
Calibre N16 decks.”
TSMC and Mentor will speak about their recent optimization
efforts in a session titled “Best Practices for Verification at
Advanced 20nm Process Nodes” in the Mentor booth #2046 at the
Design Automation Conference (DAC), Austin, Texas, June 2-5. To
register for the session, please go to the Mentor DAC web site at
http://www.mentor.com/events/design-automation-conference/.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic
hardware and software design solutions, providing products,
consulting services and award-winning support for the world’s most
successful electronic, semiconductor and systems companies.
Established in 1981, the company reported revenues in the last
fiscal year of about $1,090 million. Corporate headquarters are
located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
World Wide Web site: http://www.mentor.com/.
(Mentor Graphics and Calibre are registered trademarks and PERC
and nmDRC are trademarks of Mentor Graphics Corporation. All other
company or product names are the registered trademarks or
trademarks of their respective owners.)
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