Mentor Graphics Design and Verification Tools Certified for TSMC 16nm FinFET
29 5월 2013 - 8:00AM
Business Wire
Mentor Graphics Corp. (NASDAQ: MENT) today announced that its
Calibre® physical verification platform has achieved version 0.1 of
design reference manual (DRM) and SPICE model tool certification
for TSMC’s 16nm manufacturing process, which incorporates 3D
(FinFET) transistors for higher performance. TSMC has given 0.1
Certification to the Mentor® Olympus-SoC™ place and route system,
and the Calibre physical verification platform. The Mentor 16nm
platforms are now available to support customers with their early
16nm FinFET design efforts.
The Mentor Olympus-SoC place and route system for 16nm FinFET
enables efficient double patterning (DP) and timing closure with
comprehensive support for new design rule checks and
multi-patterning rules, fin grid alignment for standard cells and
macros during placement, and Vt min-area rule and implant layer
support during placement.
The Calibre nmPlatform product for 16nm FinFET supports advanced
design rule definition and litho hotspot pre-filtering. In
addition, the Calibre SmartFill facility was enhanced to support
the TSMC-specified filling requirements for FinFET transistors,
including support for density constraints and multilayer structures
needed for FinFET layers. The SmartFill solution also provides
double patterning support for back end layers and user-defined fill
cells that are automatically inserted into a layout based on
analysis of the design.
Reliability is also a key element of TSMC’s 16nm FinFET process
technology. FinFET 3D transistors will enable devices with higher
drive strengths than at previous nodes, so accurate reliability
verification becomes even more critical. As highlighted in the
Design Enablement section of the recent TSMC Technology Symposium,
reliability checks based upon the Calibre PERC™ platform will
enable customers to analyze and correct issues like electrostatic
discharge (ESD) and latch-up.
“With the advent of FinFET transistors, such as those used in
TSMC’s 16nm FinFET process, the fundamental geometric architecture
of IC transistors has been redefined for the first time since
Federico Faggin designed the commercial silicon-gate IC at
Fairchild in 1968,” said Joseph Sawicki, vice president and general
manager of the Design to Silicon division at Mentor Graphics.
“We’ve worked closely with TSMC to understand the impact of FinFETs
and their interaction with other innovations, such as
multi-patterning, on the physical design flow. Enhancing our
products to handle 16nm FinFET requirements transparently helps
designers stay focused on using the new process capabilities to
create more value for their customers.”
“Mentor is a longstanding contributor to the TSMC OIP ecosystem
and our on-going collaboration has resulted in the general market
availability of 16nm FinFET design kits to support our earliest
advanced technology customers,” said Suk Lee, TSMC senior director,
Design Infrastructure Marketing Division. “This successful
milestone once again confirms that foundry-EDA collaboration is
critical to driving innovation for the semiconductor design
industry.”
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic
hardware and software design solutions, providing products,
consulting services and award-winning support for the world’s most
successful electronic, semiconductor and systems companies.
Established in 1981, the company reported revenues in the last
fiscal year of about $1,090 million. Corporate headquarters are
located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
World Wide Web site: http://www.mentor.com.
(Mentor Graphics, Mentor, and Calibre are registered trademarks
and Olympus-SoC and PERC are trademarks of Mentor Graphics
Corporation. All other company or product names are the registered
trademarks or trademarks of their respective owners.)
Mentor Graphics Corp. (NASDAQ:MENT)
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