Mentor Graphics Announces the First IP to System, UPF-based Low-power Verification Solution
04 4월 2013 - 10:00PM
Business Wire
Mentor Graphics Corp. (NASDAQ:MENT) today announced availability
of the first, comprehensive IP to System, UPF-based low-power
verification flow. The IEEE-1801 UPF (Unified Power Format) has
emerged as the low- power standard that enables designers to
specify a design’s power intent separately from the design itself
ensuring reuse, portability and greater flexibility in power
management techniques. Mentor now has platform-level support of UPF
in both the Questa® functional verification platform and the
Veloce® family of hardware emulators that lets users create a
single specification for power intent that is reusable and
consistent, and facilitates low-power verification across
simulation, formal and emulation.
“Power management is a critical aspect of nearly all complex
designs today and impacts the entire design and verification flow.
UPF enables reusable and early verification of power management
architectures and ensures implementation consistent with the
specification of power intent,” said Erich Marschner, vice-chair of
the IEEE P1801 UPF Working Group and verification architect at
Mentor Graphics. “Mentor Graphics has taken a leading role both in
driving the UPF standard and working in parallel to deliver a
comprehensive and open UPF-based solution with Questa verification
and Veloce emulation. Together they deliver increased simulation
performance, new power intent debug, low-power clock domain
crossing verification and low-power emulation, enabling users to
thoroughly verify and debug all low-power aspects of their design
in a manageable IP/block to system methodology.”
Advanced Simulation, Visualization and Debug: The latest
Questa release delivers up to a 6X boost in UPF simulation
performance, which provides the horsepower needed to verify the
integration of a subsystem or full chip with its power management
architecture. This performance, combined with the new power intent
visibility in the Questa GUI and automatic low-power checks,
enables users to easily and completely verify, visualize and debug
all effects of adding the UPF to both RTL and gate level
simulations. The Questa functional verification platform also
introduces new automatic low-power coverage metrics and the
generation of a low-power test plan making it easy to include power
management coverage points to a comprehensive coverage closure
strategy. The latest release improves support and compatibility for
the open Liberty library format, which provides a smooth flow
between low-power synthesis and implementation.
Low-power Clock Domain Crossing Verification: With the
growing number of clocks in complex SoCs, clock domain crossing
verification has become critical to detect clock interaction issues
that cannot be detected in simulation-based techniques. Because UPF
introduces power intent logic that could potentially be inserted in
paths that cross clock domain boundaries, Questa CDC now reads the
UPF to automatically detect errors injected by this additional
logic, therefore ensuring low-power clock domain crossing
verification.
Verifying Power Control Software: The early validation of
software-based power control state machines requires the
performance of hardware emulation. The Veloce emulator now delivers
the most comprehensive UPF support for low-power emulation. It also
automatically synthesizes the UPF power intent logic and performs
dynamic checks for monitoring low-power functionality, alerting
users to cases of incorrect low-power behavior. Veloce now makes it
possible to run application-level software in power critical
scenarios.
“Veloce with UPF delivers the performance and capacity needed to
validate power management software,” said Eric Selosse, vice
president and general manager, Mentor Emulation Division.
“Verification and debug of this code is critical to achieving
optimal battery life on mobile devices.”
"For design teams looking for ways to reduce power, the greatest
impact can be made by implementing a low-power strategy at RTL and
above,” said Shawn McCloud, vice president of marketing, Calypto
Design Systems. “It is exciting to see that Mentor Graphics has
leveraged the UPF standard to create a new low-power flow enabling
companies to more readily adopt low-power methodologies early in
the design and verification cycle where the biggest impact can be
made.”
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic
hardware and software design solutions, providing products,
consulting services and award-winning support for the world’s most
successful electronic, semiconductor and systems companies.
Established in 1981, the company reported revenues in the last
fiscal year of about $1,090 million. Corporate headquarters are
located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.
World Wide Web site: http://www.mentor.com/.
(Mentor Graphics, Questa and Veloce are registered trademarks of
Mentor Graphics Corporation. All other company or product names are
the registered trademarks or trademarks of their respective
owners.)
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