Mentor Graphics Teams With Infineon to Deploy State-of-the-Art Verification
01 12월 2010 - 11:00PM
Marketwired
Mentor Graphics Corporation (NASDAQ: MENT) today announced it has
successfully supported Infineon to improve Infineon's verification
productivity and effectiveness by assessing the status quo and by
jointly establishing improved SystemVerilog (SV) methodologies.
Mentor supported Infineon in this deployment based on Mentor's
functional verification solutions. The cornerstone of Infineon's
new verification environment is the Questa® functional verification
platform. The technologies linked with the Questa platform, when
applied with the established methodologies, improve Infineon's
verification process.
"Infineon has the challenge of ensuring that closure is achieved
on complex designs that span multiple time zones and multiple teams
on a tight schedule. We knew in advance that we needed to make the
most of every verification cycle in order to achieve our goal,"
said Hartmut Hiller, vice president, Design Methodologies &
Implementation at Infineon. "We jointly worked with Mentor to
improve our advanced environment that allows for the electronic
association of verification requirements through every stage of the
process, linking formal results, low-power results, simulation
results and coverage information into a single data base."
This unified database was analyzed within the Questa environment
to automatically determine if closure was reached. Mentor worked
closely with Infineon in an assessment of the status quo and the
identification of the gaps compared to Infineon's solid vision of
the desired verification environment based on industry standards
such as OVM and SystemVerilog. Mentor then contributed tools,
methodology, and know-how to support Infineon to achieve its
vision. The results are already being applied on Infineon
designs.
Improving Functional Verification To
facilitate the work, Mentor supported Infineon in creating a
verification architecture document that described the overall
strategy, architecture and implementation approach that would be
taken to build the verification infrastructure. The verification
strategy document defined the general methods, layers, phases,
components, libraries, scripts, databases, tools, and decisions
that would be used throughout the verification effort. With the
fully documented verification plan, the teams had a clear picture
of how to:
- Build reusable verification components for each of the design
under test (DUT) interfaces
- Incorporate non-intrusive UPF-based power-aware logic within
the verification environment
- Incorporate automatic formal technology to ease the process of
identifying the type of bugs found via formal techniques
- Incorporate verification metrics like assertion density,
functional coverage, bug tracking, test ranking, test sorting, and
test merging to provide useful information about the verification
status, and how to monitor real verification progress in terms of
the effectiveness of each test
- Build a series of pseudo-random test case sequences via a
combination of constraints and object oriented programming (OOP)
extensions within an OVM testbench, to find bugs and exhaustively
verify the functionality of the DUT
The Results Infineon, working together
with Mentor, has further refined their advanced verification
process to a state-of-the-art process. The process structure
provides visibility and predictability into the entire verification
process, which provides confidence in the verification status of a
design. The process is expected to show significant productivity
gain as it first focuses on what is needed, and then selects the
right tools for the job. This approach also enables reuse.
The addition of Questa's power aware and automated formal
technology is exposing power related and critical corner case
issues much earlier in the verification process. "Independent of
company size, design type or end-user market, companies verifying
complex IC are facing a mounting number of functional verification
challenges," said John Lenyo, general manager of the Design
Verification and Technology division at Mentor Graphics. "The
effective deployment of advanced verification tools and processes
is required to address the complexities raised by today's complex
ASICs and SoC designs. We are pleased to partner with companies
such as Infineon, where the result of our efforts is a more
effective verification solution than either party could have
implemented on their own. We are looking forward to continued work
with Infineon to ensure their verification environment continues to
be the best the industry has to offer."
About Mentor Graphics Mentor Graphics
Corporation (NASDAQ: MENT) is a world leader in electronic hardware
and software design solutions, providing products, consulting
services and award-winning support for the world's most successful
electronic, semiconductor and systems companies. Established in
1981, the company reported revenues over the last 12 months of
about $850 million. Corporate headquarters are located at 8005 S.W.
Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site:
http://www.mentor.com/.
(Mentor Graphics and Questa are registered trademarks of Mentor
Graphics Corporation. All other company and/or product names are
the trademarks and/or registered trademarks of their respective
owners.)
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For more information, please contact: Carole Dunn Mentor
Graphics 503.685.4716 carole_dunn@mentor.com Ry Schwark Mentor
Graphics 503.685.1660 ry_schwark@mentor.com
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