Mentor Graphics and ARM Join Forces on Memory Test and Repair
01 11월 2010 - 10:00PM
Marketwired
Mentor Graphics Corporation (NASDAQ: MENT) today announced it has
teamed up with ARM to provide an automated memory test and repair
solution for ARM embedded memories and processor cores. The new
capability provides full interoperability between Mentor's
industry-leading Tessent™ memory test and repair solution and ARM's
family of cores and embedded memory IP.
"The requirements for embedded memories are increasing as design
complexity and demand for feature rich functionality grow," said
Simon Segars, executive vice president and general manager, ARM
physical IP division. "An effective memory test and repair solution
is critical to ensuring high quality levels and maximum product
yield. We are pleased to be working with Mentor to ensure a robust
memory test and repair solution is available to our mutual
customers."
In order to maximize performance, ARM now includes an optimized
memory BIST bus and interface that provides external access to all
memories contained within the processor core. This integrated
feature enables normally intrusive memory BIST IP to be placed
outside the core, removing any impact to processor performance.
Mentor's recently introduced Tessent memory BIST and self-repair
solution has been enhanced to fully support this interface. The
Tessent MemoryBIST product automatically configures, generates and
integrates memory BIST and self-repair IP that operates with an ARM
processor core's specific bus and embedded memories.
The Tessent solution also supports ARM memory compiler features.
ARM has developed the capability to generate a complete Tessent
memory view for memory instances generated by their compilers
supporting TSMC 40nm and Common Platform 32/28nm processes. This
interoperability enables a fully automated flow for adding Tessent
test and repair functionality to ARM embedded memories contained
anywhere within a design or processor core.
"With the huge complexity involved in testing the latest
processor-based SoCs, designers need as much automation as possible
to ensure that testing does not become the bottleneck in getting
new designs to market," said Joseph Sawicki, vice president and
general manager for the Design-to-Silicon division at Mentor
Graphics. "At the same time, they cannot afford to skimp on the
quality of test. This integration between Tessent and ARM
technologies gives customers what they need to deliver the most
advanced, defect-free IC products to market in a timely
manner."
Availability The Tessent MemoryBIST
product currently supports ARM memory compiler features. Automatic
generation capability of Tessent memory views, including repair
support, for ARM memory compilers for TSMC 40nm and Common Platform
32/28nm processes will be available in Q4 2010. Tessent support of
the ARM Processor core memory BIST interface will be available in
Q4 2010 within the standard Tessent MemoryBIST product.
About Mentor Graphics Mentor Graphics
Corporation (NASDAQ: MENT) is a world leader in electronic hardware
and software design solutions, providing products, consulting
services and award-winning support for the world's most successful
electronics and semiconductor companies. Established in 1981, the
company reported revenues over the last 12 months of about $800
million. Corporate headquarters are located at 8005 S.W. Boeckman
Road, Wilsonville, Oregon 97070-7777. World Wide Web site:
http://www.mentor.com/
(Mentor Graphics is a registered trademark and Tessent is a
trademark of Mentor Graphics Corporation. All other company or
product names are the registered trademarks or trademarks of their
respective owners.)
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For more information, please contact: Gene Forte Mentor Graphics
503.685.1193 gene_forte@mentor.com Sonia Harrison Mentor Graphics
503.685.1165 sonia_harrison@mentor.com
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