Mentor Graphics Outlines Strategy to Unify Silicon Test and Yield Analysis
02 11월 2009 - 8:00PM
Business Wire
Mentor Graphics Corporation (NASDAQ: MENT) today outlined its
strategy and roadmap to help customers address the growing test
challenges they face in moving to smaller process nodes and more
complex, low-power, mixed-signal systems-on-chip (SOCs). As part of
this strategy, Mentor is uniting its award-winning embedded
compression and automatic test pattern generation (ATPG) technology
with the leading built-in self-test (BIST) technology from recently
acquired LogicVision into a new product line, called Tessent™. The
Tessent line is the industry’s most comprehensive set of
design-for-test and silicon test solutions, and also includes
LogicVision’s SiliconInsight product, Mentor’s layout-aware
diagnosis tools and the newly announced Tessent YieldInsight
product to provide solutions for post-silicon test characterization
and yield analysis.
“Those who follow Mentor Graphics know that we target segments
where we can be in a strong number one position,” said Joseph
Sawicki, vice president and general manager for the
Design-to-Silicon Division at Mentor Graphics. “The combination of
Mentor’s market-leading scan-based test and yield analysis
products, and the LogicVision BIST solutions, puts us in the top
spot across the board in silicon test. We plan to grow from that
position of strength by taking the newly branded Tessent line
broader and deeper, and continuing to provide the industry’s most
complete and unified solution for silicon test, diagnosis and yield
analysis.”
“ON Semiconductor is committed to utilizing best-in-class ATPG
and BIST technologies for product development,” said Peter Zdebel,
senior vice president and CTO at ON Semiconductor. “We are
enthusiastic about the benefits that the single integrated product
line from Mentor Graphics offers. We have a longstanding
relationship with Mentor in the DFT/ATPG arena that we value and
will continue to foster. We look forward to utilizing Mentor’s
expanded silicon test and yield analysis product-line to provide
our customers with world-class products.”
Emerging Challenges in Silicon Test and Yield
Analysis
Various drivers are making design-for-test (DFT) and
implementation of production test much more difficult than in the
past. SOCs designed for 45nm processes and below with low power
requirements, embedded microprocessors and memory, as well as
analog circuitry and high-speed serial I/O, pose some extremely
difficult test challenges. As a result, customers are taking longer
to plan, implement, and bring up tests for their new ICs, and
production test times and costs are increasing. Moving to smaller
nodes also increases design sensitivity to normal manufacturing
variability, introducing systematic failure mechanisms that are
difficult to find using traditional failure analysis techniques.
This can lead to a slower ramp-to-volume production and reduced
profitability.
Mentor’s Tessent Product Line Provides a Comprehensive
Solution
Mentor’s Tessent product line addresses these new challenges
with a coherent, interoperable suite of products that combine the
best features of deterministic scan test, embedded pattern
compression, and BIST. Mentor offers the most comprehensive range
of test capabilities, which extends across all types of IC elements
(logic, memory, analog I/O), all phases of test design and
implementation (test definition, RTL insertion, test verification,
test bring-up, silicon characterization, wafer test, and package
test), and all test methodologies (ATPG, embedded compression,
BIST, boundary scan, memory repair, test failure diagnosis, yield
analysis).
Future Roadmap
Going forward, Mentor’s BIST offerings will be based on the
former LogicVision platform and the ATPG offerings on Mentor’s
TestKompress® and FastScan™ platform. Although some of Mentor’s
former BIST products and LogicVision’s former ATPG products will be
discontinued, they will continue to be supported for existing
customers until they transition to the new products. Mentor will
also continue to invest and develop mixed-signal BIST technologies
for SerDes high-speed I/O and PLL testing, as well as the
SiliconInsight® product line developed at LogicVision.
Additionally, Mentor will continue to improve the level of
interoperability of all Tessent products, to expand the Tessent
integration flow to support the latest design flows and styles, and
to add more functionality to address specific emerging challenges
related to test.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in
electronic hardware and software design solutions, providing
products, consulting services and award-winning support for the
world’s most successful electronics and semiconductor companies.
Established in 1981, the company reported revenues over the last 12
months of about $800 million and employs approximately 4,425 people
worldwide. Corporate headquarters are located at 8005 S.W. Boeckman
Road, Wilsonville, Oregon 97070-7777. World Wide Web site:
http://www.mentor.com/.
(Mentor Graphics, LogicVision, TestKompress, and SiliconInsight
are registered trademarks and Tessent, YieldInsight and FastScan
are trademarks of Mentor Graphics Corporation. All other company or
product names are the registered trademarks or trademarks of their
respective owners.)
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